1. Field of the Invention
This invention is related to a semiconductor device and a manufacturing method of the same, and in particular to a semiconductor device manufactured by multiple exposure technology and a manufacturing method of a semiconductor device which includes multiple exposure technology.
2. Description of the Related Art
Multiple exposure technology is known among semiconductor device manufacturing technologies. Multiple exposure technology is a technology in which one layout is divided into at least two or more sub-patterns and exposure is performed after separating exposure conditions for each sub-pattern. As an example of multiple exposure technology, there is a method disclosed in J. W. Park et al., “Robust double exposure flow for memory”, Proc. of SPIE, Vol. 6154, 61542E (2006). Because a buffer region in which misalignment during manufacturing is considered is necessary on a boundary between a sub-pattern and another sub-pattern, as the number of sub-patterns and buffer regions increase, the semiconductor chip area also increases. In addition, if division of a sub-pattern is not optimally performed, an exposure margin decreases leading to a decrease in yield ratios.
However, as a miniature formation technology which exceeds the resolution limits of lithography, side wall processing is known. As an example of this side wall processing, a method is disclosed in “Patterning with spacer for expanding the resolution limit of current lithography tool”, Proc. of SPIE, Vol. 6156, 61561J (2006) by W. Y. Jung et al. Side wall processing is a process which can process the finished dimensions of a pattern to below half of an exposure dimension. There are limitations to layout pattern which can be processed by said wall processing and if a circuit pattern is created which is not appropriate for side wall processing, exposure and process margins decrease leading to a decrease in yield ratios as well as an increase in the area of a semiconductor chip.